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Searched refs:CLK_TOP_APLL1_D8 (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h50 #define CLK_TOP_APLL1_D8 39 macro
A Dmt8516-clk.h60 #define CLK_TOP_APLL1_D8 36 macro
A Dmt8183-clk.h80 #define CLK_TOP_APLL1_D8 44 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c115 FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
221 CLK_TOP_APLL1_D8,
231 CLK_TOP_APLL1_D8,
A Dclk-mt8516.c102 FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
718 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
A Dclk-mt8183.c151 FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED),
502 CLK_TOP_APLL1_D8

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