Searched refs:CLK_TOP_APLL1_D8 (Results 1 – 6 of 6) sorted by relevance
/u-boot/include/dt-bindings/clock/ |
A D | mt8512-clk.h | 50 #define CLK_TOP_APLL1_D8 39 macro
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A D | mt8516-clk.h | 60 #define CLK_TOP_APLL1_D8 36 macro
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A D | mt8183-clk.h | 80 #define CLK_TOP_APLL1_D8 44 macro
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/u-boot/drivers/clk/mediatek/ |
A D | clk-mt8512.c | 115 FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8), 221 CLK_TOP_APLL1_D8, 231 CLK_TOP_APLL1_D8,
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A D | clk-mt8516.c | 102 FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2), 718 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
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A D | clk-mt8183.c | 151 FACTOR(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8, CLK_PARENT_APMIXED), 502 CLK_TOP_APLL1_D8
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Completed in 11 milliseconds