Searched refs:CLK_TOP_APLL1_SRC_SEL (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8518.c | 118 FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
119 FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
120 FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
121 FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
122 FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
289 CLK_TOP_APLL1_SRC_SEL
385 CLK_TOP_APLL1_SRC_SEL,
808 CLK_TOP_APLL1_SRC_SEL,
1232 MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt8518-clk.h | 128 #define CLK_TOP_APLL1_SRC_SEL 106 macro
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