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Searched refs:CLK_TOP_APLL2_D2 (Results 1 – 8 of 8) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h53 #define CLK_TOP_APLL2_D2 42 macro
A Dmt8516-clk.h62 #define CLK_TOP_APLL2_D2 38 macro
A Dmt8518-clk.h57 #define CLK_TOP_APLL2_D2 35 macro
A Dmt8183-clk.h82 #define CLK_TOP_APLL2_D2 46 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c118 FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
239 CLK_TOP_APLL2_D2,
A Dclk-mt8516.c104 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
719 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
A Dclk-mt8183.c153 FACTOR(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2, CLK_PARENT_APMIXED),
507 CLK_TOP_APLL2_D2,
A Dclk-mt8518.c103 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
462 CLK_TOP_APLL2_D2,

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