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Searched refs:CLK_TOP_APLL2_D8 (Results 1 – 8 of 8) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h56 #define CLK_TOP_APLL2_D8 45 macro
A Dmt8516-clk.h64 #define CLK_TOP_APLL2_D8 40 macro
A Dmt8518-clk.h60 #define CLK_TOP_APLL2_D8 38 macro
A Dmt8183-clk.h84 #define CLK_TOP_APLL2_D8 48 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c121 FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
219 CLK_TOP_APLL2_D8,
242 CLK_TOP_APLL2_D8,
A Dclk-mt8516.c106 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
721 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
A Dclk-mt8183.c155 FACTOR(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8, CLK_PARENT_APMIXED),
509 CLK_TOP_APLL2_D8
A Dclk-mt8518.c106 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
803 CLK_TOP_APLL2_D8

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