Searched refs:CLK_TOP_APLL2_SRC_SEL (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8518.c | 123 FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
124 FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
125 FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
126 FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
127 FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
294 CLK_TOP_APLL2_SRC_SEL
396 CLK_TOP_APLL2_SRC_SEL,
820 CLK_TOP_APLL2_SRC_SEL,
1233 MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt8518-clk.h | 129 #define CLK_TOP_APLL2_SRC_SEL 107 macro
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