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Searched refs:CLK_TOP_ASM_H_SEL (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h87 #define CLK_TOP_ASM_H_SEL 76 macro
A Dmt7622-clk.h99 #define CLK_TOP_ASM_H_SEL 86 macro
A Dmt7623-clk.h135 #define CLK_TOP_ASM_H_SEL 121 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c509 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
A Dclk-mt7622.c358 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
A Dclk-mt7623.c555 MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),

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