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Searched refs:CLK_TOP_ASM_M_SEL (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h86 #define CLK_TOP_ASM_M_SEL 75 macro
A Dmt7622-clk.h98 #define CLK_TOP_ASM_M_SEL 85 macro
A Dmt7623-clk.h134 #define CLK_TOP_ASM_M_SEL 120 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c506 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
A Dclk-mt7622.c357 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
A Dclk-mt7623.c553 MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),

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