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Searched refs:CLK_TOP_ATB_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h107 #define CLK_TOP_ATB_SEL 93 macro
A Dmt7622-clk.h89 #define CLK_TOP_ATB_SEL 76 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c343 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
A Dclk-mt7629.c396 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),

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