Searched refs:CLK_TOP_AUD1_SEL (Results 1 – 8 of 8) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 111 #define CLK_TOP_AUD1_SEL 97 macro
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| A D | mt8516-clk.h | 93 #define CLK_TOP_AUD1_SEL 69 macro
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| A D | mt7622-clk.h | 93 #define CLK_TOP_AUD1_SEL 80 macro
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| A D | mt8518-clk.h | 98 #define CLK_TOP_AUD1_SEL 76 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8516.c | 518 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
704 GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
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| A D | clk-mt7622.c | 307 CLK_TOP_AUD1_SEL,
350 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
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| A D | clk-mt8518.c | 1196 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
1451 GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
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| A D | clk-mt7629.c | 403 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
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