Searched refs:CLK_TOP_AUDINTBUS_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A D	mt7623-clk.h	116 #define CLK_TOP_AUDINTBUS_SEL 102 macro
/u-boot/drivers/clk/mediatek/
A D	clk-mt7623.c	530 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),

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