Searched refs:CLK_TOP_AUDPLL_MUX_SEL (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 171 FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
172 FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
173 FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
174 FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
175 FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
573 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7623-clk.h | 148 #define CLK_TOP_AUDPLL_MUX_SEL 134 macro
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