Searched refs:CLK_TOP_AUD_ENGEN1_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A D	mt8516-clk.h	95 #define CLK_TOP_AUD_ENGEN1_SEL 71 macro
/u-boot/drivers/clk/mediatek/
A D	clk-mt8516.c	520 MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2), 706 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),

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