Searched refs:CLK_TOP_AUD_K5_SRC_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A D	mt7623-clk.h	153 #define CLK_TOP_AUD_K5_SRC_SEL 139 macro
/u-boot/drivers/clk/mediatek/
A D	clk-mt7623.c	579 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),

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