Searched refs:CLK_TOP_AXISEL_D4 (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 184 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
651 GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
652 GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
653 GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
654 GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
655 GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
656 GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
657 GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7623-clk.h | 98 #define CLK_TOP_AXISEL_D4 85 macro
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