Searched refs:CLK_TOP_DMPLL (Results 1 – 11 of 11) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 86 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
149 FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
150 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
151 FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
201 CLK_TOP_DMPLL
217 CLK_TOP_DMPLL
405 CLK_TOP_DMPLL
446 CLK_TOP_DMPLL,
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| A D | clk-mt7629.c | 99 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
161 CLK_TOP_DMPLL
166 CLK_TOP_DMPLL
182 CLK_TOP_DMPLL
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| A D | clk-mt8516.c | 69 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
121 CLK_TOP_DMPLL,
737 .fdivs_offs = CLK_TOP_DMPLL,
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| A D | clk-mt7622.c | 101 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
154 CLK_TOP_DMPLL
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| A D | clk-mt8518.c | 72 FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
139 CLK_TOP_DMPLL
1493 .fdivs_offs = CLK_TOP_DMPLL,
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 34 #define CLK_TOP_DMPLL 21 macro
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| A D | mt8516-clk.h | 27 #define CLK_TOP_DMPLL 3 macro
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| A D | mt7622-clk.h | 29 #define CLK_TOP_DMPLL 17 macro
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| A D | mt8518-clk.h | 26 #define CLK_TOP_DMPLL 4 macro
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| A D | mt7623-clk.h | 13 #define CLK_TOP_DMPLL 1 macro
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| /u-boot/arch/arm/dts/ |
| A D | mt7629.dtsi | 122 <&topckgen CLK_TOP_DMPLL>;
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