Home
last modified time | relevance | path

Searched refs:CLK_TOP_ETHIF_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/dts/
A Dmt7623.dtsi135 <&topckgen CLK_TOP_ETHIF_SEL>;
268 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
360 clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
395 clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>;
436 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c557 MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
716 GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
720 GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
721 GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
722 GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
723 GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
/u-boot/include/dt-bindings/clock/
A Dmt7623-clk.h137 #define CLK_TOP_ETHIF_SEL 123 macro
/u-boot/doc/device-tree-bindings/pci/
A Dmediatek-pcie.txt76 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,

Completed in 7 milliseconds