Searched refs:CLK_TOP_ETHIF_SEL (Results 1 – 4 of 4) sorted by relevance
/u-boot/arch/arm/dts/ |
A D | mt7623.dtsi | 135 <&topckgen CLK_TOP_ETHIF_SEL>; 268 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 360 clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; 395 clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; 436 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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/u-boot/drivers/clk/mediatek/ |
A D | clk-mt7623.c | 557 MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31, 716 GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5), 720 GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11), 721 GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14), 722 GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17), 723 GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
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/u-boot/include/dt-bindings/clock/ |
A D | mt7623-clk.h | 137 #define CLK_TOP_ETHIF_SEL 123 macro
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/u-boot/doc/device-tree-bindings/pci/ |
A D | mediatek-pcie.txt | 76 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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