Searched refs:CLK_TOP_ETHPLL_500M (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 181 FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
717 GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
719 GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
727 GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
728 GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
729 GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
730 GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
731 GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
|
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7623-clk.h | 95 #define CLK_TOP_ETHPLL_500M 82 macro
|
Completed in 6 milliseconds