Searched refs:CLK_TOP_ETH_SEL (Results 1 – 10 of 10) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 90 #define CLK_TOP_ETH_SEL 76 macro
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| A D | mt8516-clk.h | 90 #define CLK_TOP_ETH_SEL 66 macro
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| A D | mt8518-clk.h | 97 #define CLK_TOP_ETH_SEL 75 macro
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| A D | mt7622-clk.h | 72 #define CLK_TOP_ETH_SEL 59 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8516.c | 111 FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
515 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
701 GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
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| A D | clk-mt7622.c | 316 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
505 GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
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| A D | clk-mt8518.c | 1195 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
1450 GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
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| A D | clk-mt7629.c | 369 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
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| /u-boot/arch/arm/dts/ |
| A D | mt7629.dtsi | 287 clocks = <&topckgen CLK_TOP_ETH_SEL>,
310 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
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| A D | mt7622.dtsi | 376 clocks = <&topckgen CLK_TOP_ETH_SEL>,
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