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Searched refs:CLK_TOP_FA2SYS_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8518-clk.h115 #define CLK_TOP_FA2SYS_SEL 93 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8518.c1216 MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
1467 GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),

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