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Searched refs:CLK_TOP_FASM_M_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8518-clk.h117 #define CLK_TOP_FASM_M_SEL 95 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8518.c1218 MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
1470 GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),

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