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Searched refs:CLK_TOP_FECC_CK_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8518-clk.h120 #define CLK_TOP_FECC_CK_SEL 98 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8518.c1222 MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
1472 GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),

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