Searched refs:CLK_TOP_HAPLL1_SEL (Results 1 – 4 of 4) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt8512-clk.h | 81 #define CLK_TOP_HAPLL1_SEL 70 macro
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| A D | mt8518-clk.h | 132 #define CLK_TOP_HAPLL1_SEL 110 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8518.c | 1238 MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
1465 GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
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| A D | clk-mt8512.c | 490 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
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