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Searched refs:CLK_TOP_I2S1_MCK_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7622-clk.h103 #define CLK_TOP_I2S1_MCK_SEL 90 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c364 MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),

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