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Searched refs:CLK_TOP_INTDIR_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7622-clk.h85 #define CLK_TOP_INTDIR_SEL 72 macro
A Dmt7623-clk.h132 #define CLK_TOP_INTDIR_SEL 118 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c337 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
A Dclk-mt7623.c551 MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),

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