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Searched refs:CLK_TOP_INT_32K_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8518-clk.h127 #define CLK_TOP_INT_32K_SEL 105 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8518.c1231 MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),

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