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Searched refs:CLK_TOP_MEM_SEL (Results 1 – 9 of 9) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h70 #define CLK_TOP_MEM_SEL 59 macro
A Dmt7629-clk.h88 #define CLK_TOP_MEM_SEL 74 macro
A Dmt7622-clk.h70 #define CLK_TOP_MEM_SEL 57 macro
A Dmt7623-clk.h102 #define CLK_TOP_MEM_SEL 88 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c511 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
606 GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
609 GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
610 GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
A Dclk-mt8512.c454 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
A Dclk-mt7622.c314 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
A Dclk-mt7629.c367 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
/u-boot/arch/arm/dts/
A Dmt7629.dtsi121 <&topckgen CLK_TOP_MEM_SEL>,

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