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Searched refs:CLK_TOP_MSDC2_SEL (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8516-clk.h89 #define CLK_TOP_MSDC2_SEL 65 macro
A Dmt8518-clk.h137 #define CLK_TOP_MSDC2_SEL 115 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8516.c514 MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
700 GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
A Dclk-mt8518.c1244 MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
1449 GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),

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