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Searched refs:CLK_TOP_MSDCPLL_D2 (Results 1 – 6 of 6) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h61 #define CLK_TOP_MSDCPLL_D2 50 macro
A Dmt8183-clk.h101 #define CLK_TOP_MSDCPLL_D2 65 macro
A Dmt7623-clk.h65 #define CLK_TOP_MSDCPLL_D2 52 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8512.c126 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
188 CLK_TOP_MSDCPLL_D2,
318 CLK_TOP_MSDCPLL_D2,
370 CLK_TOP_MSDCPLL_D2
A Dclk-mt8183.c177 FACTOR(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1,
362 CLK_TOP_MSDCPLL_D2,
373 CLK_TOP_MSDCPLL_D2
381 CLK_TOP_MSDCPLL_D2
A Dclk-mt7623.c142 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
235 CLK_TOP_MSDCPLL_D2,
256 CLK_TOP_MSDCPLL_D2,
281 CLK_TOP_MSDCPLL_D2,

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