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Searched refs:CLK_TOP_MUX_AXI (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt8183.c540 MUX(CLK_TOP_MUX_AXI, axi_parents, 0x40, 0, 2),
598 .muxes_offs = CLK_TOP_MUX_AXI,
670 GATE_INFRA0(CLK_INFRA_ICUSB, CLK_TOP_MUX_AXI, 8),
671 GATE_INFRA0(CLK_INFRA_GCE, CLK_TOP_MUX_AXI, 9),
689 GATE_INFRA0(CLK_INFRA_BTIF, CLK_TOP_MUX_AXI, 31),
693 GATE_INFRA1(CLK_INFRA_MSDC1, CLK_TOP_MUX_AXI, 4),
694 GATE_INFRA1(CLK_INFRA_MSDC2, CLK_TOP_MUX_AXI, 5),
697 GATE_INFRA1(CLK_INFRA_GCPU, CLK_TOP_MUX_AXI, 8),
698 GATE_INFRA1(CLK_INFRA_TRNG, CLK_TOP_MUX_AXI, 9),
700 GATE_INFRA1(CLK_INFRA_CPUM, CLK_TOP_MUX_AXI, 11),
[all …]
/u-boot/include/dt-bindings/clock/
A Dmt8183-clk.h120 #define CLK_TOP_MUX_AXI 84 macro

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