Searched refs:CLK_TOP_MUX_MSDC50_0_HCLK (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8183.c | 560 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, msdc50_hclk_parents, 0x80, 0, 2),
692 GATE_INFRA1(CLK_INFRA_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 2),
752 GATE_INFRA3(CLK_INFRA_AP_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 7),
753 GATE_INFRA3(CLK_INFRA_MD_MSDC0, CLK_TOP_MUX_MSDC50_0_HCLK, 8),
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt8183-clk.h | 136 #define CLK_TOP_MUX_MSDC50_0_HCLK 100 macro
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