Searched refs:CLK_TOP_PCIE1_MCU_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A D	mt7629-clk.h	117 #define CLK_TOP_PCIE1_MCU_SEL 103 macro
/u-boot/drivers/clk/mediatek/
A D	clk-mt7629.c	411 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23),

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