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Searched refs:CLK_TOP_PE2_MAC_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8518-clk.h121 #define CLK_TOP_PE2_MAC_SEL 99 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8518.c1223 MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
1473 GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),

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