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Searched refs:CLK_TOP_PMICSPI_SEL (Results 1 – 10 of 10) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h105 #define CLK_TOP_PMICSPI_SEL 91 macro
A Dmt8516-clk.h80 #define CLK_TOP_PMICSPI_SEL 56 macro
A Dmt8518-clk.h91 #define CLK_TOP_PMICSPI_SEL 69 macro
A Dmt7622-clk.h87 #define CLK_TOP_PMICSPI_SEL 74 macro
A Dmt7623-clk.h117 #define CLK_TOP_PMICSPI_SEL 103 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c339 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
390 GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
A Dclk-mt7623.c532 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
614 GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
A Dclk-mt8518.c1187 MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
1415 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
A Dclk-mt7629.c392 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
A Dclk-mt8516.c503 MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),

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