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Searched refs:CLK_TOP_RTC_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7623-clk.h124 #define CLK_TOP_RTC_SEL 110 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c541 MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
612 GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),

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