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Searched refs:CLK_TOP_SGMII_REF_1_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h120 #define CLK_TOP_SGMII_REF_1_SEL 106 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7629.c416 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),

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