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Searched refs:CLK_TOP_SLOW_MFG_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8516-clk.h92 #define CLK_TOP_SLOW_MFG_SEL 68 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8516.c517 MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
703 GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),

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