Searched refs:CLK_TOP_SPI0_SEL (Results 1 – 6 of 6) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 96 #define CLK_TOP_SPI0_SEL 82 macro
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| A D | mt7622-clk.h | 78 #define CLK_TOP_SPI0_SEL 65 macro
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| A D | mt7623-clk.h | 110 #define CLK_TOP_SPI0_SEL 96 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 523 MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
678 GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
689 GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
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| A D | clk-mt7622.c | 326 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
446 GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
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| A D | clk-mt7629.c | 141 FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
379 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
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Completed in 12 milliseconds