Searched refs:CLK_TOP_SPI1_SEL (Results 1 – 8 of 8) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt7629-clk.h | 97 #define CLK_TOP_SPI1_SEL 83 macro
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| A D | mt7622-clk.h | 79 #define CLK_TOP_SPI1_SEL 66 macro
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| A D | mt8518-clk.h | 140 #define CLK_TOP_SPI1_SEL 118 macro
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| A D | mt7623-clk.h | 141 #define CLK_TOP_SPI1_SEL 127 macro
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7622.c | 327 MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
444 GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
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| A D | clk-mt8518.c | 1248 MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
1412 GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
1434 GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
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| A D | clk-mt7623.c | 564 MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
691 GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
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| A D | clk-mt7629.c | 380 MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
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