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Searched refs:CLK_TOP_SPI3_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt8518-clk.h142 #define CLK_TOP_SPI3_SEL 120 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt8518.c1250 MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),

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