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Searched refs:CLK_TOP_SYSPLL1_D4 (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c109 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
192 CLK_TOP_SYSPLL1_D4,
213 CLK_TOP_SYSPLL1_D4,
231 CLK_TOP_SYSPLL1_D4,
283 CLK_TOP_SYSPLL1_D4,
290 CLK_TOP_SYSPLL1_D4,
375 CLK_TOP_SYSPLL1_D4,
401 CLK_TOP_SYSPLL1_D4,
414 CLK_TOP_SYSPLL1_D4,
443 CLK_TOP_SYSPLL1_D4,
[all …]
A Dclk-mt8512.c79 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
138 CLK_TOP_SYSPLL1_D4,
162 CLK_TOP_SYSPLL1_D4,
192 CLK_TOP_SYSPLL1_D4,
217 CLK_TOP_SYSPLL1_D4,
402 CLK_TOP_SYSPLL1_D4,
411 CLK_TOP_SYSPLL1_D4,
A Dclk-mt7629.c104 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
157 CLK_TOP_SYSPLL1_D4,
178 CLK_TOP_SYSPLL1_D4,
210 CLK_TOP_SYSPLL1_D4,
289 CLK_TOP_SYSPLL1_D4,
322 CLK_TOP_SYSPLL1_D4,
A Dclk-mt7622.c104 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
146 CLK_TOP_SYSPLL1_D4,
166 CLK_TOP_SYSPLL1_D4,
197 CLK_TOP_SYSPLL1_D4
260 CLK_TOP_SYSPLL1_D4,
/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h14 #define CLK_TOP_SYSPLL1_D4 3 macro
A Dmt7629-clk.h39 #define CLK_TOP_SYSPLL1_D4 26 macro
A Dmt7622-clk.h32 #define CLK_TOP_SYSPLL1_D4 20 macro
A Dmt7623-clk.h34 #define CLK_TOP_SYSPLL1_D4 21 macro

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