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Searched refs:CLK_TOP_SYSPLL4_D2 (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c111 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
194 CLK_TOP_SYSPLL4_D2,
221 CLK_TOP_SYSPLL4_D2,
232 CLK_TOP_SYSPLL4_D2,
261 CLK_TOP_SYSPLL4_D2,
A Dclk-mt7629.c114 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
206 CLK_TOP_SYSPLL4_D2,
235 CLK_TOP_SYSPLL4_D2,
246 CLK_TOP_SYSPLL4_D2,
290 CLK_TOP_SYSPLL4_D2,
A Dclk-mt7623.c117 FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
268 CLK_TOP_SYSPLL4_D2,
292 CLK_TOP_SYSPLL4_D2,
301 CLK_TOP_SYSPLL4_D2,
385 CLK_TOP_SYSPLL4_D2,
413 CLK_TOP_SYSPLL4_D2,
A Dclk-mt8512.c89 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
165 CLK_TOP_SYSPLL4_D2
176 CLK_TOP_SYSPLL4_D2
328 CLK_TOP_SYSPLL4_D2,
/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h24 #define CLK_TOP_SYSPLL4_D2 13 macro
A Dmt7629-clk.h49 #define CLK_TOP_SYSPLL4_D2 36 macro
A Dmt7622-clk.h39 #define CLK_TOP_SYSPLL4_D2 27 macro
A Dmt7623-clk.h42 #define CLK_TOP_SYSPLL4_D2 29 macro

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