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Searched refs:CLK_TOP_SYSPLL_D2 (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt8183.c82 FACTOR(CLK_TOP_SYSPLL_D2, CLK_TOP_SYSPLL_CK, 1,
90 FACTOR(CLK_TOP_SYSPLL_D2_D2, CLK_TOP_SYSPLL_D2, 1,
92 FACTOR(CLK_TOP_SYSPLL_D2_D4, CLK_TOP_SYSPLL_D2, 1,
94 FACTOR(CLK_TOP_SYSPLL_D2_D8, CLK_TOP_SYSPLL_D2, 1,
96 FACTOR(CLK_TOP_SYSPLL_D2_D16, CLK_TOP_SYSPLL_D2, 1,
224 CLK_TOP_SYSPLL_D2,
514 CLK_TOP_SYSPLL_D2,
A Dclk-mt7623.c104 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
108 FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
109 FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
110 FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
111 FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
422 CLK_TOP_SYSPLL_D2,
A Dclk-mt7629.c102 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
356 CLK_TOP_SYSPLL_D2
A Dclk-mt7622.c102 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h37 #define CLK_TOP_SYSPLL_D2 24 macro
A Dmt7622-clk.h30 #define CLK_TOP_SYSPLL_D2 18 macro
A Dmt8183-clk.h42 #define CLK_TOP_SYSPLL_D2 6 macro
A Dmt7623-clk.h29 #define CLK_TOP_SYSPLL_D2 16 macro

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