Searched refs:CLK_TOP_UART0_SEL (Results 1 – 6 of 6) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt8516-clk.h | 70 #define CLK_TOP_UART0_SEL 46 macro
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| A D | mt8518-clk.h | 84 #define CLK_TOP_UART0_SEL 62 macro
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| /u-boot/arch/arm/dts/ |
| A D | mt8518.dtsi | 105 clocks = <&topckgen CLK_TOP_UART0_SEL>,
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| A D | mt8516.dtsi | 145 clocks = <&topckgen CLK_TOP_UART0_SEL>,
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| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8516.c | 493 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
649 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
738 .muxes_offs = CLK_TOP_UART0_SEL,
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| A D | clk-mt8518.c | 1180 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
1402 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
1494 .muxes_offs = CLK_TOP_UART0_SEL,
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