Searched refs:CLK_TOP_UART2_SEL (Results 1 – 4 of 4) sorted by relevance
| /u-boot/include/dt-bindings/clock/ |
| A D | mt8516-clk.h | 108 #define CLK_TOP_UART2_SEL 84 macro
|
| A D | mt8518-clk.h | 107 #define CLK_TOP_UART2_SEL 85 macro
|
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8516.c | 535 MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
711 GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
|
| A D | clk-mt8518.c | 1207 MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
1456 GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
|
Completed in 9 milliseconds