Searched refs:CLK_TOP_UART_SEL (Results 1 – 11 of 11) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8512.c | 457 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
739 GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
740 GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
741 GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
742 GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
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| A D | clk-mt7622.c | 325 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
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| A D | clk-mt7629.c | 378 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
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| A D | clk-mt7623.c | 522 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt8512-clk.h | 71 #define CLK_TOP_UART_SEL 60 macro
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| A D | mt7629-clk.h | 95 #define CLK_TOP_UART_SEL 81 macro
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| A D | mt7622-clk.h | 77 #define CLK_TOP_UART_SEL 64 macro
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| A D | mt7623-clk.h | 109 #define CLK_TOP_UART_SEL 95 macro
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| /u-boot/arch/arm/dts/ |
| A D | mt7623.dtsi | 187 clocks = <&topckgen CLK_TOP_UART_SEL>,
198 clocks = <&topckgen CLK_TOP_UART_SEL>,
209 clocks = <&topckgen CLK_TOP_UART_SEL>,
220 clocks = <&topckgen CLK_TOP_UART_SEL>,
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| A D | mt7629.dtsi | 177 clocks = <&topckgen CLK_TOP_UART_SEL>,
190 clocks = <&topckgen CLK_TOP_UART_SEL>,
203 clocks = <&topckgen CLK_TOP_UART_SEL>,
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| A D | mt7622.dtsi | 172 clocks = <&topckgen CLK_TOP_UART_SEL>,
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Completed in 17 milliseconds