Searched refs:CLK_TOP_UNIVPLL1_D2 (Results 1 – 9 of 9) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt8512.c | 92 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
172 CLK_TOP_UNIVPLL1_D2,
201 CLK_TOP_UNIVPLL1_D2,
319 CLK_TOP_UNIVPLL1_D2,
345 CLK_TOP_UNIVPLL1_D2,
376 CLK_TOP_UNIVPLL1_D2,
413 CLK_TOP_UNIVPLL1_D2,
429 CLK_TOP_UNIVPLL1_D2,
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| A D | clk-mt7623.c | 129 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
215 CLK_TOP_UNIVPLL1_D2,
247 CLK_TOP_UNIVPLL1_D2
403 CLK_TOP_UNIVPLL1_D2,
445 CLK_TOP_UNIVPLL1_D2,
458 CLK_TOP_UNIVPLL1_D2,
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| A D | clk-mt7629.c | 118 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
177 CLK_TOP_UNIVPLL1_D2,
321 CLK_TOP_UNIVPLL1_D2,
351 CLK_TOP_UNIVPLL1_D2,
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| A D | clk-mt7622.c | 116 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
165 CLK_TOP_UNIVPLL1_D2,
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt8512-clk.h | 27 #define CLK_TOP_UNIVPLL1_D2 16 macro
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| A D | mt7629-clk.h | 53 #define CLK_TOP_UNIVPLL1_D2 40 macro
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| A D | mt7622-clk.h | 44 #define CLK_TOP_UNIVPLL1_D2 32 macro
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| A D | mt7623-clk.h | 53 #define CLK_TOP_UNIVPLL1_D2 40 macro
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| /u-boot/arch/arm/dts/ |
| A D | mt7629.dtsi | 95 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
312 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
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