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Searched refs:CLK_TOP_UNIVPLL_D2 (Results 1 – 12 of 12) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c121 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
129 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
130 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
131 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
185 FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
423 CLK_TOP_UNIVPLL_D2
A Dclk-mt8183.c113 FACTOR(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL_CK, 1,
118 FACTOR(CLK_TOP_UNIVPLL_D2_D2, CLK_TOP_UNIVPLL_D2, 1,
120 FACTOR(CLK_TOP_UNIVPLL_D2_D4, CLK_TOP_UNIVPLL_D2, 1,
122 FACTOR(CLK_TOP_UNIVPLL_D2_D8, CLK_TOP_UNIVPLL_D2, 1,
A Dclk-mt8516.c85 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
149 CLK_TOP_UNIVPLL_D2,
452 CLK_TOP_UNIVPLL_D2
A Dclk-mt8512.c91 FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
256 CLK_TOP_UNIVPLL_D2,
A Dclk-mt7622.c115 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
254 CLK_TOP_UNIVPLL_D2,
A Dclk-mt8518.c87 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
312 CLK_TOP_UNIVPLL_D2,
/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h26 #define CLK_TOP_UNIVPLL_D2 15 macro
A Dmt8516-clk.h43 #define CLK_TOP_UNIVPLL_D2 19 macro
A Dmt7622-clk.h43 #define CLK_TOP_UNIVPLL_D2 31 macro
A Dmt8518-clk.h41 #define CLK_TOP_UNIVPLL_D2 19 macro
A Dmt8183-clk.h58 #define CLK_TOP_UNIVPLL_D2 22 macro
A Dmt7623-clk.h45 #define CLK_TOP_UNIVPLL_D2 32 macro

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