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Searched refs:CLK_TOP_UNIVPLL_D3 (Results 1 – 12 of 12) sorted by relevance

/u-boot/drivers/clk/mediatek/
A Dclk-mt8183.c124 FACTOR(CLK_TOP_UNIVPLL_D3_D2, CLK_TOP_UNIVPLL_D3, 1,
126 FACTOR(CLK_TOP_UNIVPLL_D3_D4, CLK_TOP_UNIVPLL_D3, 1,
214 CLK_TOP_UNIVPLL_D3,
228 CLK_TOP_UNIVPLL_D3,
239 CLK_TOP_UNIVPLL_D3,
251 CLK_TOP_UNIVPLL_D3,
263 CLK_TOP_UNIVPLL_D3,
275 CLK_TOP_UNIVPLL_D3,
286 CLK_TOP_UNIVPLL_D3,
481 CLK_TOP_UNIVPLL_D3
[all …]
A Dclk-mt8512.c95 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
149 CLK_TOP_UNIVPLL_D3
170 CLK_TOP_UNIVPLL_D3,
200 CLK_TOP_UNIVPLL_D3,
338 CLK_TOP_UNIVPLL_D3
343 CLK_TOP_UNIVPLL_D3,
375 CLK_TOP_UNIVPLL_D3,
398 CLK_TOP_UNIVPLL_D3,
414 CLK_TOP_UNIVPLL_D3
A Dclk-mt7623.c122 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
132 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
133 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
134 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
135 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
136 FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
246 CLK_TOP_UNIVPLL_D3,
A Dclk-mt8518.c91 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
330 CLK_TOP_UNIVPLL_D3
429 CLK_TOP_UNIVPLL_D3,
475 CLK_TOP_UNIVPLL_D3
607 CLK_TOP_UNIVPLL_D3
A Dclk-mt8516.c89 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
148 CLK_TOP_UNIVPLL_D3,
A Dclk-mt7629.c121 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
350 CLK_TOP_UNIVPLL_D3,
/u-boot/include/dt-bindings/clock/
A Dmt8512-clk.h30 #define CLK_TOP_UNIVPLL_D3 19 macro
A Dmt7629-clk.h56 #define CLK_TOP_UNIVPLL_D3 43 macro
A Dmt8516-clk.h47 #define CLK_TOP_UNIVPLL_D3 23 macro
A Dmt8518-clk.h45 #define CLK_TOP_UNIVPLL_D3 23 macro
A Dmt8183-clk.h59 #define CLK_TOP_UNIVPLL_D3 23 macro
A Dmt7623-clk.h46 #define CLK_TOP_UNIVPLL_D3 33 macro

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