Searched refs:CLK_TOP_UNIVPLL_D5 (Results 1 – 14 of 14) sorted by relevance
| /u-boot/drivers/clk/mediatek/ |
| A D | clk-mt7623.c | 123 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
137 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
138 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
139 FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
193 CLK_TOP_UNIVPLL_D5,
214 CLK_TOP_UNIVPLL_D5,
232 CLK_TOP_UNIVPLL_D5,
402 CLK_TOP_UNIVPLL_D5,
444 CLK_TOP_UNIVPLL_D5,
459 CLK_TOP_UNIVPLL_D5,
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| A D | clk-mt7629.c | 126 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
158 CLK_TOP_UNIVPLL_D5,
179 CLK_TOP_UNIVPLL_D5,
323 CLK_TOP_UNIVPLL_D5,
353 CLK_TOP_UNIVPLL_D5,
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| A D | clk-mt8512.c | 99 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
320 CLK_TOP_UNIVPLL_D5
412 CLK_TOP_UNIVPLL_D5,
430 CLK_TOP_UNIVPLL_D5
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| A D | clk-mt8183.c | 116 FACTOR(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5, CLK_PARENT_TOPCKGEN),
130 FACTOR(CLK_TOP_UNIVPLL_D5_D2, CLK_TOP_UNIVPLL_D5, 1,
132 FACTOR(CLK_TOP_UNIVPLL_D5_D4, CLK_TOP_UNIVPLL_D5, 1,
134 FACTOR(CLK_TOP_UNIVPLL_D5_D8, CLK_TOP_UNIVPLL_D5, 1,
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| A D | clk-mt7622.c | 124 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
147 CLK_TOP_UNIVPLL_D5,
167 CLK_TOP_UNIVPLL_D5,
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| A D | clk-mt8518.c | 95 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
321 CLK_TOP_UNIVPLL_D5
345 CLK_TOP_UNIVPLL_D5,
458 CLK_TOP_UNIVPLL_D5,
495 CLK_TOP_UNIVPLL_D5,
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| A D | clk-mt8516.c | 93 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
472 CLK_TOP_UNIVPLL_D5
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| /u-boot/include/dt-bindings/clock/ |
| A D | mt8512-clk.h | 34 #define CLK_TOP_UNIVPLL_D5 23 macro
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| A D | mt7629-clk.h | 61 #define CLK_TOP_UNIVPLL_D5 48 macro
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| A D | mt8516-clk.h | 51 #define CLK_TOP_UNIVPLL_D5 27 macro
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| A D | mt7622-clk.h | 52 #define CLK_TOP_UNIVPLL_D5 40 macro
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| A D | mt8518-clk.h | 49 #define CLK_TOP_UNIVPLL_D5 27 macro
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| A D | mt8183-clk.h | 60 #define CLK_TOP_UNIVPLL_D5 24 macro
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| A D | mt7623-clk.h | 47 #define CLK_TOP_UNIVPLL_D5 34 macro
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