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Searched refs:CLK_TOP_VDEC_SEL (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7623-clk.h106 #define CLK_TOP_VDEC_SEL 92 macro
/u-boot/drivers/clk/mediatek/
A Dclk-mt7623.c517 MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),

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